I'm writing this because I think there is insufficient documentation (HRM and EE-384) on SPI Master Boot and had to infer this from experimentation. Hopefully, these notes save someone else some head scratching.
The HRM lists SPI Master Boot BCODE values. Revision 0.3 indicates values 0xA through 0xE leverage quad mode.
The following results were obtained by testing with the adi_rom_Boot() mask ROM call.
Something not documented is that the mask ROM forcibly rewrites non-volatile settings in the SPI flash via the 01h (Write Status Register) command if 05h and 35h (Read Status Registers) do not indicate that the Quad Enable bit is set.
Silicon 0.1 had the undocumented errata that it would *always* perform this non-volatile write on every single boot. This would exhaust write-cycles in systems that employed frequent booting. Silicon 1.0 seems to have remedied this.
This forced rewrite adds 10s of milliseconds to the boot time (since it must wait for the part to erase). A power failure during this could leave the SPI flash in an indeterminate state.
This forced rewrite also will potentially clear security bits that the user has set.
For Silicon 1.0, the forced rewrite in BCODE values 0xA through 0xD takes the form of a 01h 00h 02h command.
For Silicon 1.0, the forced rewrite in BCODE 0xE takes the form of a 01h 40h command.
Study the datasheet of your SPI flash to see what unintended consequences these writes may do. IMHO, it is desirable to set Quad Enable manually before invoking any of these boot modes so as to hopefully deter the mask ROM from changing the settings on your SPI flash.