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AD9578 dev board inconsistencies with data sheet

Question asked by cosmolittle on Jul 6, 2016
Latest reply on Jul 11, 2016 by SteveBeccue

Dear Steve,

     Thank you for answering my previous questions.


I am just completing my prototype board, and have noticed some inconsistencies between the development board and the data sheet:


1/-  The PLL filter capacitors are specified in the data sheet as 220nF, however on the development board 22nF capacitors are fitted.

I presume that the value of these affects the PLL closed loop bandwidth. However there is no provision for changing other components in the loop filter, so presumably only a small range of values for these capacitors will give a loop with adequate phase margin.

I was disappointed to see that the AD9578 is not included in either ADIsimCLK or ADIsimPLL. So it is not possible to investigate the effect of changing these capacitors.


2/- In the data sheet, the 6 VDDA pins are not individually described. However on the development board the decoupling of these pins is treated differently. Pins 5 and 31 have a ferrite bead between the pin  and the decoupling capacitors. Pins

12,25,37, and 48 go directly to the decoupling capacitors. Why is this done?

  On my board I currently have connected all 6 VDDA pins to a power plane which is decoupled at multiple places to the ground plane without the ferrite beads. I am also using completely different regulators and ground planes for the AD9578 output power supplies.


3/- My final reference arrangement is a single ended HCMOS input to XO2, attenuated to give a 0 to 1.8V LVCMOS voltage swing.

    The external reference is a 50MHz low phase noise VCXO locked to a low phase noise 10MHz  OCXO using an ADF4002. ADIsimPLL predicts a phase noise for the external reference as follows:


Phase Noise Table 

Freq Total  

1.00 -95.50 

10.0 -112.3

100 -120.3

1.00k -146.0

10.0k -163.0

100k -164.8 

1.00M -165.0 


This is very much lower phase noise than the 25MHz external reference you used to determine the  phase noise plots in the data sheet. However as I do not have the normalised PLL parameters for the AD9578 chip, I cannot model the final phase noise from the AD9578 outputs. Are these normalised parameters available?




Cosmo Little