I am programming AD9854 through parallel port via FPGA. As an initial test, I intended to generate a single tone sine wave. But, I could'nt.
Then I decided to just change Updated clock register value and by probing I/O UD see if I could first write into buffers and then to see if it is transfered to the right register or not. It is somehow a read back.
The configuration is as follows:
The only pin which is floated is the I/O UD pin. The 50MHz onboard crystal is being used as a clk source. By default value (40 at register 19) the internal upadate clock should clock each 2.6us. I wanna change it to 80 that can double the UD clock peiode to 5.2us.
The PMODE and RDB pins are set high. OSK pin is grounded.
The MRESET is activated for about 15 Clk cycle. Then, data and address are set up for 20ns with WR inactive(high). Then, keeping the address and data the WR signal becomes active for 20ns. Afterwards, all data and address vanish and write signal becomes inactive. But, no change in the UD clock periode.
So, I am wondering if my write timing diagram is correct or not.
Actually, I tried many different timing. For instance setting up the address, then after 20ns setting up the data and then keeping all, activate the write signal..........
Do I need to write into all bytes of the Update clock register? If so, from which byte should I start?
Or should the data and address values be kept till the update clock transferes the values from buffers into registers or once they are written they can vanish from the input pins?
Is the initial value of WR signal important?
Please, suggest me the suitable timing diagram.
Even for the single mode generation, I first wrote into TW1 register then attempted to change register 20 to inactivate the OSK EN bit and setting up the OSK INT bit. Each is happening in 2.6us intervals.
Please, let me know if there is any tricky point or something that is not mentioned in datasheet.
Anyway, Thank you in advance