AD9739 work at mix mode , can output RF signal,with center frenquency at 1.7GHz, and bandwidth = 300MHz? AD9739 Clk frequency is 2GSPS
About connection DB0(1) to UltraScale FPGA - input data for DB0(1) is LVDS, instead GTH bank's output is CML. So, you need convert CML to LVDS. Problem of this solution is to use FPGA with a lot numbers or GTH outputs (28 pairs). More simply connect input pins DB0(1) of AD9739 to ordinary FPGA LVDS output pins. You should send data to DAC througt this LVDS pairs at 625 MSPS.
Second answer - you right about clocks signals for DAC: you send to input pin DACCLK reference clock 2.5 GSPS and send to input pin DCI 625 MSPS accomplaine frequency for data signals DB0(1). When DCI = '0', DAC read data vector from data bus DB0 and when DCI = '1', DAC read data vector from data bus DB1.
The part can do that, yes, but the image will be very close to the desired signal. It would be easier to filter if you ran a higher DAC update rate, like 2.5 GSPS. Then, the image would be about 800 MHz away.
Thank you for your reply!
There is another question that the AD9739's DB0[13:0] and DB1[13:0] bus shuld be connect to Kintex UltraScale FPGA's HP bank? or GTH bank?
If the DAC update rate is 2.5 GSPS, the DCI clock is equal to 625MHz，is it right？
forward to your reply, thanks!
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