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FMCADC5 ref design failing?

Question asked by arnoldb on Jul 5, 2016
Latest reply on Jul 5, 2016 by DragosB

I am attempting to run the reference design for the AD-FMCADC5-EBZ FMC Board on a Xilinx VC707 carrier. After some stalled attempts I have discovered that (as of July 5th, 2016) the github/hdl/ 'dev' branch appears to have the latest Vivado v2015.4.2 release design, and the github/no-OS/ '2016_R1' branch has the most up-to-date microblaze code. (the current no-OS 'dev' branch will not compile under SDK v2015.4.2)

Unfortunately, I am finding that the FPGA/SW combination above seems to be failing with the following errors in the UART console window:

SYSREF Calibration Failed!!

ADC Core Initialized (156 MHz).

ADC Core Initialized (156 MHz).

ADC PN Status: 0, 1, 0x02!


Does anyone have any advise on what is going wrong?