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ADV7441 LLC output

Question asked by XAVICH on Aug 1, 2011
Latest reply on Aug 4, 2011 by GuenterL

Dear Sr,

 

      I'm using ADV7441 to convert video input to RGB 30 bits output and send this bus to FPGA. I have one problem with output video clock (LLC pin). ADV input is a 720p60Hz input format. When LLC pin is not connected (open condition) I have a output signal clock of 74.25MHz with almost 4.5V peak to peak. Waveform shape is almost squared -> Same wafeform that can be seen on evaluation board.

    When this pin is connected to FPGA through a 47 ohms resistor, waveform shape becomes almost triangular and voltage level drops to 3.3V. We checked input pin on FPGA and we tried with different input technologies. Seems that any impedance adjustment is set, only buffering. Is it possible to adjust ADV output in order to handle FPGA input? Has somebody experienced this phenomenon?

 

  Please, find attached pictures with oscilloscope captures for open pin condition and for connection to FPGA with 47 ohms resistor.

 

  On evaluation board, this pin is directly connected to Xilinx FPGA?

 

    Thanks!

 

Xavi

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