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Export to hardware for MicroBlaze SDK design from Vivado

Question asked by Intec_H on Jul 1, 2016
Latest reply on Jul 12, 2016 by CsomI

hi all,

 

Currently our group are migrating the reference design for fmcomms1 eval. board from Vivado 2014.2 to Vivado 2016.1, because the Vivado 2016 supports the parallel synthesis etc. Besides, to make the incremental design more valuable, we split the whole design into two parts: core and FE. The core contains MicroBlaze, some cpu_interconnect IPs and ddr etc. as shown below, the FE contains the front-end such as AD9122, AD9643, AD9643_dma etc. And then on a higher hierarchy a top_module uses both parts.

core_bd.png

 

To ensure the correct connection for AXI-interface between core and FE IPs, some AXI masters and slaves and memory map should be properly defined. As shown in the figures below, in Vivado 2014.2 design which contains only one block design. The axi_ad9643_dma/m_dest_axi  pin is the axi-master of axi_ddr_cntrl IP.

 

(1) The design in Vivado 2014.2

the microblaze and ddr are defined as :

set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.3 sys_mb]

set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb

set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb

 

set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.1 axi_ddr_cntrl]

set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]

file copy -force $ad_hdl_dir/projects/common/kc705/kc705_system_mig.prj "$axi_ddr_cntrl_dir/"

set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl

 

create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi]  \ [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl

 

Vivado_2014_design.png

export hardware for sdk as .hdf file:

 

(2)  Vivado 2016.1

          (a) Core

Microblaze and ddr are defined as:

set sys_mb [add_ip_cell xilinx.com:ip:microblaze:9.6 sys_mb]

set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb

set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb

 

set axi_ddr_cntrl [add_ip_cell xilinx.com:ip:mig_7series:3.0 axi_ddr_cntrl

set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]

file copy -force ../common/kc705_system_mig.prj "$axi_ddr_cntrl_dir/"

set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl

 

ad9643_dma_m_intf is defined as slave:

set ad9643_dma_m_intf    [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 ad9643_dma_m_intf]
connect_bd_intf_net -intf_net axi_mem_interconnect_s02_axi [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_ports ad9643_dma_m_intf]
set_property -dict [list CONFIG.DATA_WIDTH {128}] [get_bd_intf_ports ad9643_dma_m_intf]

 

assign_bd_address [get_bd_addr_segs {axi_ddr_cntrl/memmap/memaddr }]

    set_property offset 0x80000000 [get_bd_addr_segs {ad9643_dma_m_intf/SEG_axi_ddr_cntrl_memaddr}]

set_property range $sys_mem_size [get_bd_addr_segs {ad9643_dma_m_intf/SEG_axi_ddr_cntrl_memaddr}];

          (b) FE

ad9643_dma_m_intf is defined as a master:

set ad9643_dma_m_intf    [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 ad9643_dma_m_intf]

    set_property -dict [list CONFIG.DATA_WIDTH {128}] [get_bd_intf_ports ad9643_dma_m_intf]

 

  set sys_mem_size1 0x40000000

  assign_bd_address [get_bd_addr_segs {ad9643_dma_m_intf/Reg }]

  set_property offset 0x80000000 [get_bd_addr_segs {axi_ad9643_dma/m_dest_axi/SEG_ad9643_dma_m_intf_Reg}]

  set_property range $sys_mem_size1 [get_bd_addr_segs {axi_ad9643_dma/m_dest_axi/SEG_ad9643_dma_m_intf_Reg}];       

 

          (c) Top module connects the core and FE

connect_bd_intf_net    [get_bd_intf_pins core/ad9643_dma_m_intf] [get_bd_intf_pins FE/ad9643_dma_m_intf]

assign_bd_address [get_bd_addr_segs {core/ad9643_dma_m_intf/SEG_axi_ddr_cntrl_memaddr }];

 

export hardware for sdk as .hdf file:

 

 

Problem:

Vivado 2014.2 :The bitstream and sdk software worked well.

Vivado 2016.1: The bitstream and sdk software worked except the acess from axi_9643_dma to axi_ddr_cntrl. However, the bitstream generated by Vivado 2016 worked perfect with the sdk software 2014 (hardware profile for sdk exported from the design of Vivado 2014), even at the ddr access. So, the bitstream generated by Vivado 2016.

 

ps, the adc samples are dumped in ddr via axi_9643_dma, and then read in the sdk software from ddr to the pc via uart.

 

Note: in the .hdf file (hardware profile exported from Vivado), that exported from Vivado 2014 has sys_ilmb_cntlr and two axi_ddr_cntrl, but that from Vivado 2016 lacks of these.

 

I thought, the .hdf file is not properly exported from Vivado. Or is there any bug in Vivado 2016 or SDK 2016?

Or in our case of axi sub-system and different hierarchies, is there something that we ommited in our design?

 

 

any suggestion?

Thanks a lot.

 

Haolin

 

rejeesh dpu

 

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