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CLK1 and CLK2 values for a ramp in ADF4158

Question asked by electrosoni on Jun 30, 2016
Latest reply on Jul 1, 2016 by rbrennan


I need to generates a very quick frequency sweep and, according to the calculations, values for CLK1 and CLK2 are 1.

Both, the ADF4158 PLL software and the ADIsimPLL give a remark/error when both CLK dividers are set to 1. But in the tests I've done,  I am able to get that ramp with the right time and frequency sweep.

What is the problem in having those CLK = 1??  What kind of behaviour could I see if both CLK are set to that value?


Thanks in advance.