Is it possible to run the AD9680 1GSPS (the one on the FMCDAQ2 eval board) at a lower sample rate? 500MSPS? Is it possible to get it to 300MSPS?
The sampling rate of the AD9680 (1250MSPS, 1000MSPS, 820MSPS or 500MSPS) is set at test. once it is fused, the biases are set to be optimized for a certain sample rate. That does not mean that you cannot run a AD9680-1000 at 500MSPS for example. It just wont be as power efficient as the AD9680-500.
As for decimation ratio, this applies to the operation of internal digital down converters (DDC) that takes advantage of the "oversampling and then decimating" principle. You can read this article to get an understanding of the benefits of oversampling and decimating.
Not your Grandfather’s ADC: RF Sampling ADCs offer Advantages in Systems design
To change the sampling rate, I think that you need to change the clock setting within the Xilinx axi_jesd_gt core too. This is referenced in the user guide here, AD-FMCDAQ2-EBZ User Guide [Analog Devices Wiki] , when the statement is made that "you need to set the JESD204B rates at HDL compile time". I've seen this question come up in various ways on this forum, but I have yet to see a clear response from Analog Devices on how a change in sampling rate should be accomplished. Enough people have asked for help on this that I think they should prioritize their effort to provide clear guidance on this topic.
Here are a couple of related discussions on this topic:
Changing FMCDAQ2 Clock Frequencies
Changing AD9144 JESD204B IF Speed on FMCDAQ2
Thanks for the reply Umesh,
Is the sampling rate not also set in part by the ADC chip itself? The datasheet refers to a "chip decimation ratio" but I am unsure if this actually changes the sample rate or if its something else
Retrieving data ...