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ADC clock and data synchronization on fmcdaq2 board

Question asked by on Jun 29, 2016
Latest reply on Jul 6, 2016 by rejeesh



i'm developing a digital demudolator with fmcdaq2 board and kc705. I'm testing it with a custom ip block (called seq_generator) generating a binary sequence, trasmitted over a gpio pin of the board (kc705) and then sampled by adcs of daq2 board. the seq_generator input clock is the adc's out data clock (250 MHz) and generates also a signal to trigger the data capture. the sequence is repeated every N clock cycle (programmable) set as 2 kHz as default (125000 clock cycles)


Fore some reasons the sampled sequence shows a non-constant delay respect of the starting of capture but it's shifted at every power-up of the board (few random samples differences, about from 1 to 32 samples). The temporal distance between subsequent sequences is correct (125000 clock cycles). I use as reset of my seq_generator the signal rx_rst from axi_jesd_gt block to reset the sequence generator and i expect to have always the sampled sequence starting at the same sample.


Can i expect to have constant delay on my sampled data (i.e. seeing my sequence starting always at Nth sample) or there is some adc's feature that prevents my expectations?


any thoughts?


thank you and best regards,


Maurice Saccani