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DMA memory not aligned with data from SPI

Question asked by johnmurray on Jul 29, 2011
Latest reply on Aug 11, 2011 by johnmurray

I have setup a DMA transfer for the data I am receiving over SPI, but the data in memory is constantly shifting as if it is constantly copying the data to memory without taking the SPIDS slave-select line which is driving when the transfer occurs into account.

Either that or there is some misalignment in the setting up of the DMA and so it is shifting where it starts writing the momroy to.

Either way, I can not rely on the first byte of my memory address to be the header of the transfer packet.

 

I have tried setting different settings for CHPASE and CLKPL but this does not make a difference.

I have also tried setting differnt values for *pIMSPI which also does not fix the problem.

 

We are sending packets of data, and the first byte is header which specifies the type of data being tranfered and the length of the data.

So I need the first location in memory to contain the first byte that is transfered when the SPIDS line goes LOW/ACTIVE.

 

Seting CPHASE to 0 should then start the DMA when the signal goes LOW. And a DAM interrrupt should be raied once the transfer is complete and the destination buffer is full, and the SPIDS line goes HIGH again.

 

Unfortunatly the data is constantly shifting around in the destination buffer. I can not rely on the first byte to contain the header.

 

I have the same problem occuring with ping pong DMa buffers and a single DMA buffer.

 

I am using DPI pin 5 for the SPIDS signal (SPI_CS)

SRU (LOW, DPI_PBEN03_I);
SRU (DPI_PB03_O, SPI_CLK_I);

//Generating Code for connecting : DPI_PIN3 to SPI_MOSI
SRU (LOW, DPI_PBEN01_I);
SRU (DPI_PB01_O, SPI_MOSI_I);

//Generating Code for connecting : DPI_PIN5 to SPI_DS
SRU (LOW, DPI_PBEN05_I);
SRU (DPI_PB05_O, SPI_DS_I);

//Generating Code for connecting : SPI_MISO to DPI_PIN2
SRU (HIGH, DPI_PBEN02_I);
SRU (SPI_MISO_O, DPI_PB02_I);

 

I am setting up my DMA (non ping pong):

 

*pSPICTL = RXFLSH;
*pSPICTLB = RXFLSH;

*pSPIDMAC = FIFOFLSH;

*pIISPI = (int)destination;
*pIMSPI = 1;
*pCSPI = N;

*pSPICTL =  SPIEN | WL32 | TIMOD2 | MSBF;

*pSPIDMAC = SPIDEN | SPIRCV | INTEN;

 

Should the internal memory address modifier be 0?

 

How can I check that the DMA transfer begins when the DS signal goes LOW?

How can I ensure that the first byte of the transfer goes to the first byte of my destination memory address?

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