I received questions from our customer.
(1)What is "one-deep delay"?
Which priod is "one-deep delay" on Fig4 in the datasheet, for example?
(2)Do we need the SCK for 8 channels when we use only 2 channels?
(1) ADAS3023 has Configure register which is a 16-bit register to program the ADAS3023 to select its option like channel select, gain, reference etc. This 16 bit data will be written through the DIN pin after the End of Conversion simultaneously when the data from SDO is being read. Once the CFG (configuration register) is written, the user options that was set or written on the CFG register will not take effect immediately on the next conversion but it will take effect only after the next conversion. That means, after the CFG is written, it will experience two Start of conversion (SOC) and an EOC. The next conversion process after the SOC-EOC-SOC occur, the CFG will take effect. I have no idea why it is called one deep but the idea here is that it has a one cycle delay ( SOC-EOC-SOC) for the CFG to take effect. The picture below will show the timing diagram that pictures the summary of what was discussed, that the CFG (N) will take effect on Conv 3. There is one SOC-EOC-SOC occur then the CFG (N) will take effect on Conv 3.
(2) The ADAS3023 conversion can be read through the SDO pin and is clocked out by the SCK rising edges. It will take 16 SCK rising edge to read the result of one channel with MSB first. If there are only two channels, I think it only need 32 SCK rising edge to read the result of the two channels.
I am attending in to this thread. I'll get back to you.
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