I'm using the ad6676ebz to capture data from the adc then store them into the DDR3. I'm using the reference designs HDL and no-os software version 2015_R1. Everything works fine with the default configuration of the AXI_DMAC (64-bit master AXI).
Now, beside adc data I'm trying to store also some additional bits into the DDR, I have to change the source and destination axi data bit width to 256, the fifo write clock is 200 MHz then the adc_capture() function get stuck at "Wait until the current transfer is completed"
while(reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT));
Please let me know if the IP AXI_DMAC supports master AXI data width larger than 64 bits along with 200 MHz fifo write clock?