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ad6676ebz adc_capture with 256-bit master AXI get stuck

Question asked by Tuan.Truong on Jun 23, 2016
Latest reply on Jun 23, 2016 by larsc


Hi,

I'm using the ad6676ebz to capture data from the adc then store them into the DDR3. I'm using the reference designs HDL and no-os software version 2015_R1. Everything works fine with the default configuration of the AXI_DMAC (64-bit master AXI).

Now, beside adc data I'm trying to store also some additional bits into the DDR, I have to change the source and destination axi data bit width to 256, the fifo write clock is 200 MHz then the adc_capture() function get stuck at "Wait until the current transfer is completed"

do {

  adc_dma_read(AXI_DMAC_REG_IRQ_PENDING, &reg_val); 

  }

  while(reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT));

Please let me know if the IP AXI_DMAC supports master AXI data width larger than 64 bits along with 200 MHz fifo write clock?

Many thanks:)

 

Best Regards.

Tuan

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