i use adisimpll 4.01
pfd100MHZ freq out:15.4~15.6G frac mode
loop bandwidth :100khz phase margin:60deg
but it can't lock
did not lock to within1.0kHz
did not lock to within 10Hz
If you look at the time simulation you can see that the loop is starting to lock but the simulation is not being run for long enough:
Extend the simulation by changing the 'Stop Time' to say 200us:
and it will lock:
This loop has lots of cycle slipping and with the 60 deg phase margin the lock time estimate (used to automatically generate the Stop Time) is a bit low.
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