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Valid FpllClkout Range for  AD-FMCDAQ2-EBZ Reference Design?

Question asked by MacP on Jun 22, 2016
Latest reply on Jun 23, 2016 by AdrianC

When I examine the default settings used in the AD-FMCDAQ2-EBZ Reference Design for the axi_jesd_gt transceiver core it looks like they will set fPLLCLKout to 5GHz.  This is in between the valid ranges for the CPLL and the QPLL according to the Xilinx ug476, 7 Series Transceiver guide equations 2-1 and 2-3.  Am I missing something or is this intentional?

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