I would like to works AD9361 in TDD and LVDS condition.
I read "AD9361_Reference_Manual_UG-570.pdf" which is described timing charts condition below,
I can not find description about LVDS TDD. But this document is written as below,
When LVDS mode is used:
•Data port signaling is differential LVDS, allowing up to12-inch PCB traces/connector interconnects between theAD9361 and the BBP.
•Only the data port (including clocking and otherassociated timing signals) is LVDS compatible.
•Both FDD and TDD operation are supported.
Could you tell the timing chart in TDD LVDS condtion ?