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AD9361 TDD LVDS Digital Interface

Question asked by Taira on Jun 22, 2016
Latest reply on Jun 28, 2016 by Vinod

Hi all

 

I would like to works AD9361 in TDD and LVDS condition.

I read "AD9361_Reference_Manual_UG-570.pdf" which is described timing charts condition below,

+CMOS FDD

+CMOS TDD

+LVDS FDD

I can not find description about LVDS TDD. But this document is written as below,

--

When LVDS mode is used:

•Data port signaling is differential LVDS, allowing up to12-inch PCB traces/connector interconnects between theAD9361 and the BBP.

•Only the data port (including clocking and otherassociated timing signals) is LVDS compatible.

•Both FDD and TDD operation are supported.

--

Could you tell the timing chart in TDD LVDS condtion ?

 

BR,

Taira.

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