I am designing a stereoscopic headmounted display (HMD) and depending on the ADV7619 capabilities I may or may not need to add an FPGA (or dedicated shift registers/muxes/switches...) in my design. Schematic design can not proceed until I resolve the (possibly undocumented capability) of the ADV7619.
On page 26 of UG-237 the section of the output pixel formatter states:
Appendix C contains tables describing some of the pixel port configurations.
I will first describe the HMD a bit more, and then illustrate how in stereoscopic mode the ADV7619 has a very desirable characteristic (odd pixels on first bus, and even pixels on the second), and then the issue with monoscopic operation.
The HMD will drive 2 identical LCD panels with native resolution of 1920x1080@60Hz. Including porches the pixel clock for a single screen is 1936x1272x60Hz=147.75552MHz.
If possible I wish to support both stereoscopic and monoscopic 24-bit 1920x1080p 60Hz(per eye) HDMI input modes since this is the native resolution of the LCD. When operating monoscopically the HMD should display the single incoming signal on both screens.
The HMD will use a pixel-alternating 3D HDMI mode (as opposed to a line alternating, or field/frame alternating mode):
Pixel stream: [L1][R1][L2][R2][L3][R3]... The incoming pixel clock will be a 2x1936x1272x60Hz=295.51104MHz within 300MHz limitation of the ADV7619. As it is above 170MHz:
On a single clock edge, the first bus outputs information about odd pixels and the second video bus outputs information about even pixels.
So the first bus will output exactly the LEFT pixels, and the second bus the RIGHT pixels at the desired lower LCD pixel clock of 147.75552MHz i.e.:
first bus: [L1][L2][L3]...
The busses can be routed directly to the IC's driving the LCDs. Note that the two busses are capable of simultaneously individually operating at 147MHz. So far so good.
The HMD receives a monoscopic HDMI signal of 147.75552MHz, Is it possible to have the incoming signal be cloned/repeated output on bus 1 and 2 (given that as seen in stereoscopic mode they could actually output at these rates), such that the pixels are not interleaved, but copied, i.e. P[0..23]==P[24..47]==current incoming HDMI pixel? The PCB layout topology, component count would be lower and timing requirements easier to achieve for design of 3D capable display devices.
The reason for monoscopic mode is to lower power consumption and computational load on the HDMI source (mobile computer) when the end-user does not need 3D display, and wishes to conserve power while still having a monoscopic display.
I was kind of hoping that perhaps the design engineers thought of this use-case possibility, and perhaps undocumented quirk I2C writes could enable this behaviour?
If you can verify that it is not possible with ADV7619, consider this a suggestion for a next iteration/chip.
If you find out it is possible to enable such behaviour, I would be delighted to know how.
(I had considered using the CSC matrix entries to make a "double" identity matrix so as to cause a copy, but as far as I can tell it seems impossible with the exposed CSC documentation)
(alternatively if it is possible to have ADV7619 to produce ouput pixel repetition such that -at the resulting pixel rate of 295.5MHz- they are alternated again across bus 1 and 2.)