I need externally sync a HMC7043. The datasheet is not really clear on the limits and the state of the outputs.
What happens to the outputs during sync? I need the outputs to be glitchless during sync. They can hold at high or low while they sync but they cannot generate runt pulses.
In this case the sync pulse will come from an FPGA. What are the timing requirements for the sync pulse? Can it be in a different time domain non-integer as long at it meets the hold time? It looked like on the HMC7044 it had to be in the VCO domain. In this case we are running an agile clock of .5 to 1GHz into the HMC7043 from a DDS so this is hard to do.