Is there a way to simulate the DPLL part inside the AD9548? Using, for instance, the ADIsimPLL tool or any other suitable software package?
Given that the AD9548 PLL's loop bandwidth is generally quite low, and that the noise performance is almost entire governed by the frequency of the system clock, we didn't add the AD9548 to SimPLL. What aspect of PLL performance are you looking to model?
In fact I have already ordered the Eval Board. But waiting for it I wanted a way to check the best settings for my application thru some simulation.
I am mainly interested in the lock time values for my application. As I mentioned in a previous message for my application: I have the reference signal coming as pulsed sinusoidal (single tone) with pulse duration of 4 µs and at random frequency of 100-200 MHz. The pulse is repeated every 2 ms.
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