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What is the downside of lowering the loop filter bandwith in a PLL system?

Question asked by JChavez on Jun 17, 2016
Latest reply on Jun 20, 2016 by rbrennan


Hello everybody,

 

I am using ADF4116+CVCO33CL-0390-0410 to generate 400MHz from 10Mhz as beacon and I'm having some troubles with spurs. I'm increased the current CP to 1mA and increased the PD frequency to 10MHz (max) and  it got better (still bad for my application), so I think my loop filter bandwidth is wider than I need.

Therefore, I am planning to decrease the loop filter bandwidth and I have a few question about this.

 

Decreasing it will affect spurs? Can the bandwidth be as low as possible or there is a limit? I know it will affect my lock time but I don't really care, I only need the best possible phase noise and the least power in the spurs.

 

Also, do you the think that the bandwith loop filter is really the problem?

 

Thank you so much for your attention!

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