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AD7173-8 and multiple channel sampling

Question asked by gmetaxas on Jun 17, 2016
Latest reply on Jul 21, 2016 by gmetaxas

Hi everyone, I am trying to use AD7173-8 in an application where 3 channels are to be used and I am a little confused about that.

In particular:

  • The AD7173-8 is connected to a microcontroller via SPI. I have configured SPI according to the datasheet and communications are OK. The SPI clock frequency that I am currently using for tests is 2 MHz and I intend to push it further, if necessary. Data read from the ADC are seen on the DOUT/~RDY pin of the ADC.
  • ADC configuration details:
    • Only 3 channels of the ADC are enabled; the rest are disabled on power-up.
    • ADC MODE:SING_CYC bit is set, mode: continuous conversion, delay after channel switch: 0 us
    • IF MODE / DATA STAT: enabled for testing
    • Two setups are used (0 and 1); in setup 0, output is offset binary and in setup 1 output is unipolar.
    • Two filter configurations are used (0 and 1); in FILTCON0, sinc5+sinc1 is used and ODR is 10417 samples/s - in FILTCON1, sinc3 is used and ODR is 20.01 samples/s (this is for sampling a temperature sensor output that does not change fast)
    • External reference (ADR4533, +3.3 V) is used and external buffers (AD8572) are placed between analog voltages and ADC, thus input buffers are disabled; clock is provided by an external crystal at 16 MHz
  • The microcontroller reads the data register of the ADC at regular time intervals (upon overflow of a timer).
  • Having only one channel enabled, everything works OK. I can read data into the microcontroller's registers and they correspond to the known analog voltage values that are present each time. I read 3+1 = 4 bytes (3 with data and 1 with the contents of the STAT register).
  • When I try to enable two channels, I read 2x(3+1) = 8 bytes that correspond to successive readings of the data register. I notice that, when stepping through the microcontroller's code, the first 4 bytes correspond to one of the two ADC channels and the remaining 4 are rubbish (0xFFs); however, the STAT register contents indicate that sometimes one channel is read, sometimes the other.

 

What I want to do is to have a consistent way of reading all enabled channels of the ADC. The datasheet says about the DOUT/~RDY pin that goes low to indicate that a conversion has been completed. Up to now, when hooking a 'scope to check logic levels on the SPI lines, I cannot see DOUT/~RDY going low right after an SPI transaction; it remains high and then it goes Hi-Z (green trace is ~CS, yellow trace is DOUT/~RDY):

scope_1.png

Has anyone a suggestion to move forward? What exactly should I have to do to switch channels fast enough without losing data?

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