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AD9361: Setting TX LO causes loss of MCS?

Question asked by jtrimble on Jun 16, 2016
Latest reply on Jun 20, 2016 by mhennerich

Hello,

 

We're using two AD9361's in Multi-Chip Sync configuration for 4-channel coherent RX.  We've noticed that setting the TX LO frequency causes a momentary drop-out in RX data across the bus from the AD9361, (e.g. adc_valid_i0 coming out of the axi_ad9361 core in the Zynq deasserts for some time) which seems to indicate that setting the TX LO frequency breaks the MCS relationship between our AD9361's.

 

We are using the linux driver (circa adi-linux xcomm_zynq commit 89b8d4e99) and writing to one of the 9361s' "out_altvoltage1_TX_LO_frequency" parameter under IIO sysfs.  It appears that large changes in TX LO frequency (e.g. over 100 MHz) seem to cause the drop-out in RX data reliably.

 

Is this intended behavior?  Is there a way to tune the TX LO without requiring subsequent MCS re-synchronization?

 

Also, longer-term, would it make sense for the AD9361 driver to provide a pollable sysfs attribute that will be sysfs_notify()'ed in the kernel when the driver takes an action that would invalidate a previous MCS operation (and thus allow userspace to react by re-establishing MCS)?

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