We have certain errors on the receive path of AD9361. It is used in TDD mode and with LVDS interface to the baseband. With a given value of DATA_CLK Delay programmed in register 0x6, the receive is perfect in FDD mode operation. However when we use the same hardware in TDD mode, there are receive IQ errors that creep in. Adjusting the value of Rx Data Delay seems to eliminate these errors but it is inconsistent.
One pointer is, the receive is error-free for some time and then again with errors. This inconsistent behavior on the receive path is what prompted us to try different values of "Rx Data Delay" to accommodate for any board path delays.
The Enable and TXNRX signals meet the timing requirements as specified in the datasheet.
We are unable to understand the difference in behavior on account of "Rx Data Delay" as this behavior is to be identical irrespective of TDD mode or FDD mode.