It seems the maximum AD9361 RX gain is not about 70 dB as specified in the data sheet. My configuration is as floowing:
1. FDD at 460MHz and BW=4.35MHZ;
2. Use IIO Slow AGC default setting
3. The RSSI value on FPGA is -10 dB FSR when RX input signal is -30dBm. This seems the slow agc is functioning.
4. The RSSI value on FPGA is -14 dB FSR when RX input signal is -70 dBm. If input 4dBm is corresponding to -2 dB FSR, this seems the maximum RX gain is about 62 dB. Ths gain is about 8dB short.