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a problem of the reference HDL design for FMCDAQ2-EBZ with KC705

Question asked by Xu-Kevin on Jun 14, 2016
Latest reply on Jul 21, 2017 by justinklchan

Hi,I have been struggling to build the reference HDL design for FMCDAQ2-EBZ with KC705.

AD-FMCDAQ2-EBZ HDL Reference Design [Analog Devices Wiki]

The above link is the reference HDL design.

I downloaded all the file needed.

Then I followed the ADI Reference Designs HDL User Guide at ADI Reference Designs HDL User Guide [Analog Devices Wiki]  to build libraries and project on Vivado.

After building all the libraries , I tried to use the TCL script to  run the project.

But it can't generate bit file.

And the TCL console messeges are as follows:


error copying "daq2_kc705.runs/impl_1/system_top.sysdef": no such file or directory

    while executing

"file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top.hdf"

    invoked from within

"if [expr [get_property SLACK [get_timing_paths]] < 0] {

    file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top_..."

    (procedure "adi_project_run" line 26)

    invoked from within

"adi_project_run daq2_kc705"

    (file "./system_project.tcl" line 19)


Then I tried to run implementation manually,the error is ,


[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:

i_system_wrapper/system_i/axi_ad9144_jesd/inst/i_system_axi_ad9144_jesd_0 (jesd204_v6_1_top)

i_system_wrapper/system_i/axi_ad9680_jesd/inst/i_system_axi_ad9680_jesd_0 (jesd204_v6_1_top__parameterized0)


The  branche of the HDL file I used is  Master.

How to fix the problem?