Thanks for your clicking
I am trying to get the 20Mbps data in BBP from AD9361, I use CMOS, FDD,DDR,Full duplex,Full prot mode, and configure the related register use AD9361 evaluation software.It can work successfully in most of the time.
However, sometime(after rewrite to FPGA), I received 40Mbps data, and duty of DATA_CLK is not 50% but is 25%.
Does anyone meet these questions? Why it happend and how can sovle it.
Thx a lot!!