I am using AD-FMCDAQ2-EBZ, Xilinx KCU105 and bare metal software. (https://wiki.analog.com/resources/eval/user-guides/ad-fmcdaq2-ebz/software/baremetal)
I can see that from the DAC side samples are arranged to four 16 bit blocks from 63 down to 0.
From the side ADC the received MSB bits are not always in position from 63 down to 48 as in send DAC data, but sometimes their place will be drifted down to bits [47:32], [31:16] or [15:0], depending how bare metal software has started. Is this issue related to how the JESD204 lanes are synced together, maybe the word sync is missing or what could cause this?
If I reset the bare metal software I can see that the received ADC data will change its order how the 16 bit blocks are received.