It looks to me that you have the TDM signal set to tri-state for unused channels correct?
There is a digital bug in the part that will gate the clock output when the TDM output goes to tri-state. The workaround is to not tri-state the TDM.
If you need to combine the signal from two parts then you can run the data through the part and assemble the TDM stream that way. I can explain more if this is indeed what you are doing.
hi Dave, you are right, i used tdm mode to get 8 channel adc input. clock output is ok now when i writing 0x00 in the SOUT_CONTROL0 registers. thank you very much.
The problem is NOT that you are using TDM8, it is that you are tri-stating the unused channels. This control is located in the Serial Port Control Register 1, bit 7. Make sure bit 7 is set low and the clock output will be fine. You can do TDM 8 with this part.
So if you have two ADAU1372 parts, you can daisy chain the serial ports so that one of them will feed the four ADC signals out of ADC_SDATA0 port in TDM 8 mode, into the second part's DAC_SDATA port.
Then internally inside the part you will route the data back out of the ADC_SDATA0 port of the second part. You can arrange the channels any way that works for you. in the second part you can take the ADCs and feed them to channels 0-3 of the TDM data. Then take channels 0-3 coming into the DAC_SDATA and feed those to channels 4-7 of the TDM. Then you will end up with eight channels of TDM with data from 8 ADCs. I expect you will see one sample period of delay from the four channels coming from the first part so you will have to adjust that in the DSP if you require simultaneous sampling.
Look at Figure 50 in the datasheet and you will see what is possible.
Retrieving data ...