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ADV7619 settings for in 2x24-bit 4:4:4 SDR interleaved mode

Question asked by gubuyu on Jun 13, 2016
Latest reply on Jun 15, 2016 by gubuyu


Hi,

   I am using an ADV7619 to receive 3840*1080 @60Hz ,3840*2160@30Hz and 2560*1600@60Hz HDMI signals. Its' pixel bus is configured in 2x24-bit 4:4:4 SDR interleaved mode.The pixel bus is connected to an FPGA.

  In 2x24-bit 4:4:4 SDR interleaved mode, i change gray scale of source image  frome 0-255 ,but only grayscale value "0-16 and 255 " is stable ,others are not stable. if current gray scale of source image is m, the output value of ADV7619 is changed between m and m+1,sometimes is m+2.

   I  tried some other resolutions with pixel clock frequencies below 170 MHz,including 1080P.the output of ADV7619 are all right and stable. But only in 2 × 24-bit SDR Mode,the output is unstable.

  I also changed HDMI cable,it has no effect.My Hdmi cable is 2.0v ,and support 4K2K resolution.

   All the settings refer to script "ADV7619-VER.1.9c.txt" .I do not have an evaluation board.

 

i red registers as shown below,

98  6F  01 ;

98  6A  53 ;

68  04  23 ;

68  05  80 ;

68  07  AF;

 

That means clock  sync de and data  are locked.

 

  Why is that?

  Give me some useful ideas,please! Thanks very much!

 

  Best Regards,

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