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PZSDR TDD module questions

Question asked by pzsdr-user on Jun 13, 2016
Latest reply on Jun 24, 2016 by charlyelkhoury

A few questions about the PicoZed SDR Dev Kit TDD personality module (AD-PZSDR2400TDD-EB).


  • The module user guide [1] indicates the PAs of each channel are controlled by different GPIO signals. However according to the rev B schematics the PAs are controlled by a common signal (RF_GPIO0, level-shifted and duplicated as RF_GPIO0_5V and RF_GPIO1_5V). The Zynq-driven RF_GPIO1 signal is not used. This is an unfortunate restriction - is a version of this module with independent PA control planned?


  • The datasheet [2] for the level shifter at U15 that generates the RF_GPIO0_5V and RF_GPIO1_5V signals specifies abs max Vcc as 4.6v; the module connects Vcc to 5v. Is this an actual problem in hardware or just an error in the public BOM?


  • The level shifter at U16 [3] is supplied by 5v and is shifting the AD9361_GP[0:3] signals driven by the PZSDR AD9361 whose VDDA_GPO = 2.5v. This means the level shifter's V_ih and AD9361 GPO V_oh are both 2.0v, leaving zero margin for power supply variations or trace losses?


  • The PZSDR SOM drives connector JX4.9 with VDDA_GPO_PWR, the supply that sets the AD9361 GPO output voltage. The FMC carrier connects JX4.9 to the personality module header P3.18 as net AD9361_GPO_VDD. The TDD personality module connects the matting connector P2.18 to AGND. Have I overlooked something? I can't see how the GPO signals can work if the VDDA_GPO_PWR rail is shorted to GND.


[1] ADI wiki:

[2] Fairchild NC7WV16P6X:

[3] TI SN74LV4T125: