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AD7712: /DRDY stays high after 1st read

Question asked by TWA on Jul 26, 2011
Latest reply on Jul 27, 2011 by MaryMc

Hello,

 

This is about receiving data register contents from AD7712.

 

The problem is that AD7712 cannot set /DRDY pin low after 1st read on data register. I would like my system to read data register continuously.

 

The 1st read terminated when AD7712 turned on /DRDY right after the last falling edge of SCLK. Then, /DRDY pin seems to remain high afterward. Thus, AD7712 can send out data register content only once in my configuration.

 

I have followed the procedures in Figure 16 and 17 in the spec sheet(rev F). Would it be helpful if some oscilloscope shots or snippets of source code are uploaded?

 

The procedure I have used:
1. poweron
2. write control register (to enable 24-bit reading)
3. read control register (to check if control reg is written correctly)
4. read data register (was ok)
5. read data register (failed due to /DRDY never being low again)

 

What I have noticed/done:
1. Since the power-on, /DRDY's been low until the end of 1st read
2. Since the beginning of 1st read, A0's been set high all the way thru the beginning of 2nd read. Not sure if its ok. Need to turn AO on once the read/write finished?
3. At the end of 1st read, /RFS is set high after /DRDY becomes high.

 

config:
    +5V on ref in+
    GND on ref in-
    external clocking at 9.8304MHz (to MCLK IN)
    bipolar input on AIN1
    AIN2 unused
    mode to gnd
    standby to +5V

 

control register setting:
    operating mode = normal, MD2=0, MD1=0, MD0=0
    pga gain = 1, G2=0, G1=0, G0=0
    channel selection = AIN1 low-level input, CH=0
    power-down = normal, PD=0
    word-length = 24-bit, WL=1
    reserved = 0
    burnout current = off, BO=0
    bipolar/unipolar selection = bipolar, B/U = 0
       
    filter selection, FS11-FS0, 12-bit, d1920

 

Best Regards,
Tetsuya

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