I am using the Linux driver along with hdl_2015_master to configure the AD9361. The AD9361 (arradio) is connected with Alter SocKit. I would like to transmit of the custom data so I have created a FIFO buffer which passes 64 bit to the util_dac_unpack_channels_data_dma_data[63..0] in hld_2015 master design. I have checked the the transmitted data on the spectrum analyzer and it shows me the correct spectrum but the amplitude is quite less. The maximum amplitude is around -45db and also the carrier signal also has an amplitude of -50db. So, I am receiving the signal with high bit errors rate.
When i send the same coefficient by using the IIO GUI, by uploading the .mat file under FPGA settings I get a maximum amplitude for the same coefficients of -30db.
So could you please tell me how can i get the same response of the amplitude when i am passing the data through a buffer as i have mentioned above?
I have also one more query for the receiver in the same configuration but without the transmitting buffer. I am capturing the siganl on adc_pack_channels_data_ddata[63..0] using signal tap analyzer in Quartus 15.0. I would like to know, if I capture the signal on ADI IIO oscilloscope and also on signal tap analyzer does it start any internal routine which changes the data on both sides or the data is always the same irrespective where I capture?
Is it okay if capture on both sides (ADI IIO Oscilloscope on GUI and Signal tap analyzer Quartus 15.0) at a same time?