I am using FMCOMMS3 board with ZYNQ ZC702. I am using reference design with small modification in it. I am transmitting at the rate of 82 KBps. To test my PL blocks,I gave steps(10,20,30,40,50,60...) input at Tx end. When I am checking data received which digital loop back(Digital Tx-> Digital Rx), I am getting exact same data as transmitted which shows all connections are proper. But when I loop it back by cable in analog domain, Sometimes I get it correct, but when I change my carrier frequency or sampling period it changes its shape and misses few steps. Even though my rate of change of data is too slow(82 KBps) and sampling is too high(30MSPS) why this is happening? Is there any special setting is required?