Memory Error Protection Unit (MEPU) handles single-bit/double-bit memory error detection/correction across the memories in the chip and controls routing of their interrupts/triggers. Memory error interrupts generated in one core can be routed to the other cores using MEPU.
It consists of following blocks
- Memory Error Controller (MEC)
- Parity Controller (PCTL)
- ECC Controller (ECTL)
The SHARC+ core in ADSP-SC57x/2157x supports Single Error Detection scheme in all of its internal RAMs (L1CACHE, BTB and L1). Parity Error detection to Peripheral RAMs is also supported. Any parity interrupt can be directly routed to the core in which the error is detected through the Core Event Controller (as in ADSP-SC58x/2158x) or routed through MEC and SEC to any of the three cores.
Similarly ECC error generated in L2CTL can be routed directly through SEC alone (as in ADSP-SC58x/2158x) or through MEC and SEC combined. The provision of routing ECC interrupts through MEC was added in case we add ECC to other memories apart from L2 also in the future. At the same time we wanted to retain backward compatibility with ADSP-SC58x/2158x and hence the direct connection of L2 ECC interrupt to SEC is retained