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How to understand the AD9361 TX/RX FIR sample clock rates?

Question asked by c3commsystems on Jun 9, 2016
Latest reply on Nov 4, 2016 by Vinod

Hi,

 

On AD9361 UG-570 page 31, it says: " The Tx FIR uses DAC_CLK as its sample clock. ... The Tx FIR calculates 16 taps per clock cycle ..."

 

Note that between the DAC and the TXFIR, there are HB1, HB2, and HB3. Does this mean that, if TX FIR is used, we must bypass those three half band filters?

 

A similar question can be asked regarding the RX FIR, as being said on UG-570 page 34, " The Rx FIR has two options for its sample clock, either ADC_CLK or ADC_CLK/2." Again, there are three half band filters that, if not bypassed, can bring the input sample rate to RX FIR down to ADC_CLK/8 or ADC_CLK/12.

 

Thanks!

Z.C.

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