Does the ADV7393 generate HSYNC and VSYNC on its own with out the external sync either directly on the two pins or thro the embedded timing codes of SAV and EAV ?
The data sheet is a bit confusing. Pl clarify
Without any input timing, how would the part know what video format to output? Or are you asking if the parts internal test pattern generator does this?
The clarification needed is
In SD master mode, does it generate the HSYNC and VSYNC internally ?
Or one of the two modes is essential, that is either the embedded timing codes in SAV and EAV or external HS and VS to be inputted on the pins.
What is the difference in slave mode and master modes in SD ?
If the part generates the SD timing on its own, the video data can be inputted to the device.
Is my question clear.
There are several master modes-- there is one where the ADV7393 generates H and V synchs and outputs them on the pins. It never generates EAV/SAV-- those are input data lines. One of the other master modes outputs H and F and the H/V pins which could be used to make EAV/SAV codes by the user.
If you use that master mode, you don't need to generate synchs yourself.
The slave modes expect you to generate the timing, and the different modes give you different options for generating timing.
modified thread to reflect ADV7393 rather than AD7393.
Thank you for your reply.
I need further clarification in continuation.
In master modes in SD when the ADV7393 generates the H and V/F signals, what is the format of the data to be given on the 16 data lines ?
Let me elaborate this question.
Is it adequate if data starts with the Y,Cb/Cr ?
What data should be given during blanking intervals ?
Is it essential to include SAV/EAV codes in the data or they are not required ?
I understand that in master modes, the complete timing is internally generated. The only input used by the IC is the CLKIN. Is my understanding right ?
Based on your reply, I may have furhter queries.
The data sheet is not very explicit on this or I may have missed it.
Is there any confusion with my question.
The data sheet doesnt seem to be very clear on some of the options possible.
Same problem was there for ADV7171 also.
Is there any application note giveing all the details ?
In master mode, the part expects YCbCr data as defined in the mode you are using... 16-bit mode normally means Y and either CB/CR per video clock. Any data during the blanking region will be ignored, so you can put anything. EAV/SAV is not needed when H/V synchs are used.
CLKIN and the Data bus would be needed in master mode.
I'm afraid I'm not aware of any application note that would be more explicit, the data sheet isn't very specific but part of that is that the timing is based on an input signal that is a SMPTE standard, so the standard timings would apply.
Thank you for your prompt reply.
Board configuration, design and realization is a long procedure. That is why I would like to ensure that my understanding is right.
From the clarifications given by you and the data sheet timings for modes 0 to 3, I understand the following.
Data is anyway input in all the modes 0 to 3 and in both master and slave.
1. In slave mode 0
Data pins: The 8/10/16 bit data should be input to contain the SAV and EAV timing codes and the appropriate horizontal and vertical blanking data also. (as per figure 104 of the data shhet)
HSYNC and VSYNC pins: No signals need to be input. They should be tied to Vdd io.
2. In slave modes 1 to 3
HSYNC and VSYNC pins: Appropriate signals (HS, VS/F) should be input.
Data pins: Only image data (Y,Cb/Cr) needs to be input.
During the slot for SAV/EAV timing codes and blanking (horizontal and vertical) intervals, no specific data needs to be input. Any junk data present would be ignored by the chip..
3. In Master modes 0 to 3
HSYNC and VSYNC pins: Appropriate signals (HS, VS/F) would be output by the chip. These timing signals would be generated by the chip using the 27 MHz CLKIN signal and the settings in the control registers. Data lines are not used to generate these signals
During the slot for SAV/EAV timing codes and blanking (horizontal and vertical) intervals, no specific data needs to be input. Any junk data present would be ignored by the chip.
4. Differences in modes 0 to 3
They are in terms of the polarity and timing of HS and VS/F only.
In master modes 0 to 3 and slave modes 1 to 3, the data to be input is the same as in 2 and 3 above.
Only in slave mode 0, the data input must contain the SAV/EAV and blanking interval data alng with the image data.
Pl confirm if this is right or anything is missing.
That is a pretty good summary, it appears correct.
This info can be explicitly added in the data sheet for the benefit of others.
Many of the current data sheets are not clear and comprehensive as the old intel data sheets used to be.
Thank you once again for your support
This should read ADV7393? Is this correct?
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