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How to reduce fpga clock interference at DDS/PLL output spectrum?

Question asked by soumyabumba on Jun 8, 2016
Latest reply on Jun 12, 2016 by LouijieC

I am using a Xilinx Spartan 6 FPGA to control a DDS AD9914. The FPGA clock is 50 MHz and the higher order clock harmonics are appearing as spurs in the DDS output. How to take care to reduce the fpga clock interference at the output spectrum to reduce these control clock related spurs? Will isolating the gnd beneath the crystal will be enough or any isolators / metallic sheilding are to be used?