Set to LVDS DDR FDD mode , sent by the FPGA 120MHz clock and data to the AD9364 , AD9364 and then loop back to the FPGA. According to datasheet timings , send the following : I_MSB (6bits), Q_MSB (6bits), I_LSB (6bits), Q_LSB (6bits). But FPGA receives is I_LSB (6bits), Q_LSB (6bits), I_MSB (6bits), Q_MSB (6bits). That is, high and low 6 6 swap the position data . But if the same configuration I have to reconfigure it again, results may be normal , and then configure it again , it might swap the position .
I do operate as follows:
1.0x3F5 set 0x01, that is set to loopback mode
2. Adjust the 0x007 and 0x006 delay , we found nothing to help
3. My FPGA clock and data output to meet the data sheet timing requirements
4. Find the following registers related to :
That is : D7, D0 0x011 and the 0x012 of . Wherein , D0 functions described as:
However, after I set up two register value (0x011 = 0x80,0x012 = 0x13) findings still wrong , did not play any role .
In this regard, I can not explain , please help , thank you !