The AD9910 data sheet (Rev. C) specifies the SYNC_CLK as output clock divided by four on Table 3. Is it refering to the system clock as output clock.
In the parallel port data modulation mode the parallel data clock, PDCLK, is generated which is specified to be 1/4 the DAC sample rate.
In DDS the DAC is clock is generally the system clock.
If this is the case then both SYNC_CLK and PDCLK will be 1/4 the system clock.
Why are there two output signals that run at the same frequency (1/4 the system clock).