I'm trying to simulate the AD fcmdaq2 project using the behavioral simulation. The goal is to understand the system and then to edit it but some errors appeared:
ERROR: [VRFC 10-1374] size mismatch in mixed language port association, vhdl port mem_a [C:/***/***/***/hdl-master/projects/daq2/kc705/daq2_kc705.srcs/sources_1/bd/system/hdl/system.v:6990]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
(settings: Target simulation : Vivado simulator; simulator language: Mixed)