I would like to convert 480x240 HDMI to RGB, but my PC outputs 9.2 Mhz TMDS CLK instead of pixel repetition. Is it possible to lock the TMDS PLL to this slow clock somehow?
We are looking in to your question.
HDMI specification calls for a minimum TMDS clock signal of 20MHz. My initial answer would be no, the ADV7612 was not designed with 9.2MHz as a design constraint. However we never tested there so I do not have a definitive answer. My recommendation would be to purchase a ADV7612-7511P evaluation board and try it out.
Advantiv™ EVAL-ADV7612-7511 Video Evaluation Board
I tried in the development board, but the pll could not be locked without pixel repetition.
According to the ADV7612 Reference Manual page 47, avi infoframe should contain pixel repetition information, and in this case 68 05 register of the ADV7612 should containt 2x instead of 1x.
Is there any example script for the pixel repetition?
The ADV7612 determines pixel repetition from the AVI info frame it receives. If the source is sending 480i then it should have 2x pixel rep putting the clock rate greater than 20MHz. However the HDMI receiver will receive 480i at 13.5MHz even though this is out of spec range. Need to check the source and make sure is is really sending at 27MHz, not 13.5MHz.
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