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DDC Problem on FMCDAQ2

Question asked by 0dBc on Jun 5, 2016
Latest reply on Jan 3, 2017 by CsomI

I am having a lot of trouble with AD9680 driver. First of all, the driver is very very limited in terms of configurability. The ADC itself is so configurable, but the driver is only works for the default case of Full Bandwidth mode. In my application, I need to sample two independent channels and downconvert the samples to baseband I&Q, decimate the I&Q outputs by two. My questions are:


1) What is the order of the I/Q data at the JESD output on the FPGA side? There are 128 bits coming out of JESD RX core.

Since I have four virtual converters, there must be two samples per converter. My guess is as follows:

adc_data_0 = {QA[1], QA[0], IA[1], IA[0]}

adc_data_1 = {QB[1], QB[0], IB[1], IB[0]}

Here I named the converters as IA, QA, IB and QB. IA corresponds to I data of the channel A, QA corresponds to Q data of the channel A and so on.


2) The only mode I can get working is the default mode given in the driver, the full bandwidth mode. If I turn on any of the DDCs, the data becomes very noisy, and there are lots of spurious.  See the attached graph. The graph was taken with an input signal at 271MHz. NCO is set to 250MHz.


My test setup:


Driver software: No-OS



For register values and the modifications I did in the No-OS driver files, see the attached no-OS_driver_Modifications.txt file.


I appreciate your earliest response.