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AD9364 / AD9361 Spurious signal improvement

Question asked by Bro-veloper on Jun 3, 2016
Latest reply on Jun 6, 2016 by tlili


My coworkers and I are currently evaluating the RF performance of the AD9364 on the AD-FMCOMMS4-EBZ board. Our application is test & measurement and therefore spectral purity (spurious free dynamic range (SFDR)) is important to us.


We have observed spurious content at 8dB (0MHz offset), 13dB (-8.48MHz offset), etc above a noise floor of -137dBm with no signal input.


Correct me if I'm wrong but my understanding is that these spurs are caused by the source used to clock the ADCs in the AD9364. Therefore, the (im)purity of the ADC_CLK is the cause of the spurs, which could be either from the PLL used to generate ADC_CLK or the source driving the PLL, such as the external crystal populated at Y101 (Epson outd-2b-0166). Is this correct?


My question is, can we improve/reduce the spurs by changing the reference from the Epson XTAL (used on the demo board) to a external clock, oscillator or clock generator/distributor device with better jitter/phase noise specifications?

Is it possible to reduce the spurs to the point where they are below the 140, 150, 160dBm noise floor?


Also, if we want to inject a high quality external reference/oscillator into Y105 (REF_CLK) to see if this improves the spurious content during our evaluation phase, do we need to depopulate the Epson XTAL (Y101)?


Thank you