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Can you clarify the RX paralell data format?

Question asked by htorke on Jun 3, 2016
Latest reply on Jun 10, 2016 by rejeesh

The AD9361 is supposed to have a 12 bit ADC. In the FPGA HDL file, the axi_ad9361 has tx and rx busses which run 16 bits. How is the data being transmitted here? Is it signed? 2's complement? And if so, is it packed to the MSB with hanging zeros or to LSB with sign extension?

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