In an application with a small SMPS, it is intended to have the GND of the primary side electronics (including the metering) just behind a common mode suppression choke (NOT the GND of the power switching circuitry itself).
This means that the measuring reference for the ADC's has some common mode AC difference to the GND of the metering, due to DC resistance of the common mode choke.
The datasheet states:
A common-mode voltage of less than ±25 mV is recommended. Common-mode voltages in excess of this recommended value may limit the available dynamic range.
How is this limitation expressed? On the low side of the dynamic range? I.e. very small differential signals get an error offset due to limited CMRR (which is not specified in the datasheet). Or is it expressed on the high side of the dynamic range? I.e. the sum of full scale signal and CM-level exceeding any linearity?
BTW: it is expected that the mains frequency AC voltage between GND of metering chip and common point of measuring (one leg of the choke) is limited to approx. 70 mV.
Of course, it is quite logical to share the GND of the metering chip with the common measuring point for voltage and current measurement, but by putting the chip's GND behind the choke I'd expect better robustness related to EMC.