AnsweredAssumed Answered

I don't see the right HS and VS signals in ADV7842 composite output

Question asked by jmunoz on Jun 3, 2016
Latest reply on Oct 13, 2016 by jmunoz

Hi everyone,


I need configure the adv7842 as composite input for PAL/NTSC and I need to have the horizontal and vertical syncs active to '1' during all blanking area


I have configured my device with the "scripts 1CVBS" I have found in VER.5.9c_AVEB.txt


I have added some lines at the end of that scripts to have YCbCr 20bits output


In my board I have the adv7842 connected to a FPGA, and the output of the FPGA to a video processor


The issue is I don't have the right hs/vs signals in the adv7842 output


I have tried to change the value of SDP 0x94, 0x95, 0x96, 0x97, 0xA8, 0xA9, 0xAA and 0xAB but I don't have the right syncs


For example, for 0x95/0x94 I read in the datasheet... "The number applied to the register offsets the HSync pulse position

with respect to the default value "


But where can I find the default value?


Could anybody help me with this issue? I am working fine with HDMI and DVI inputs


Thank you in advance


PD: My scripts


adv7842_write(0x40, 0x00, 0x01); // CVBS 4x1 mode
adv7842_write(0x40, 0x01, 0x00); // SD core
adv7842_write(0x40, 0x0C, 0x40); // Power up Core
adv7842_write(0x40, 0x15, 0x80); // Power up pads
adv7842_write(0x40, 0x19, 0x83); // LLC DLL phase
adv7842_write(0x40, 0x33, 0x40); // LLC DLL enable



adv7842_write(0x4C, 0x00, 0x0E); // ADC0 power Up
adv7842_write(0x4C, 0x02, 0x80); // Manual Mux
adv7842_write(0x4C, 0x03, 0xB0); // Ain11
adv7842_write(0x4C, 0x0C, 0x1F); // ADI recommended write
adv7842_write(0x4C, 0x12, 0x63); // ADI recommended write 


adv7842_write(0x94, 0x7A, 0xA5); // Timing Adjustment
adv7842_write(0x94, 0x7B, 0x8F); // Timing Adjustment
adv7842_write(0x94, 0x60, 0x01); // SDRAM reset
adv7842_write(0x94, 0x97, 0x00); // Hsync width Adjustment
adv7842_write(0x94, 0xB2, 0x60); // Disable AV codes


adv7842_write(0x90, 0x00, 0x7F); // Autodetect PAL NTSC SECAM
adv7842_write(0x90, 0x01, 0x00); // Pedestal Off
adv7842_write(0x90, 0x03, 0xE4); // Manual VCR Gain Luma 0x40B
adv7842_write(0x90, 0x04, 0x0B); // Manual Luma setting
adv7842_write(0x90, 0x05, 0xC3); // Manual Chroma setting 0x3FE
adv7842_write(0x90, 0x06, 0xFE); // Manual Chroma setting
adv7842_write(0x90, 0x12, 0x05); // Frame TBC,3D comb enabled
adv7842_write(0x90, 0xA7, 0x00); // ADI Recommended Write


adv7842_write(0x40, 0x02, 0xF2); // added
adv7842_write(0x40, 0x03, 0xC1); // 10-bit PAR mode 0
adv7842_write(0x40, 0x04, 0x42); // P[35:24] U/CrCb/B, P[23:12] Y/G, P[11:0] V/R
adv7842_write(0x40, 0x05, 0x28); // 
adv7842_write(0x40, 0x06, 0xA6); //