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ADV7441 LTA bit definition

Question asked by takashima.i54 on Jun 2, 2016
Latest reply on Jun 7, 2016 by joe.triggs


Currently I review the register settings of the ADV7441A refer the ADV7441A SOFTWARE MANUAL.

Regarding the LTA[1:0] in 0x27 Pixel Delay Control, SOFTWARE MANUAL described as below.

- 0 0  No Delay

- 0 1  Luma 1 clk (37ns) delayed

- 1 0  Luma 2 clk (74ns) early

- 0 1  Luma 1 clk (74ns) early

Why this description has two 0 1 settings?

I think that we need to set 1 1 to select Luma 1 clk (74ns) early.

Am I correct?

 

Please reply as soon as possible.

 

Best regards,

Takashima

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