I am having trouble getting the modified reference design work with a custom carrier board built around the Xilinx Kintex Ultrascale 115 (XCKU115).
The initialization proceeds as expected until the initialization of the JESD_GT.
At that point, I get the following message for each lane:
JESD204B-GT-RX[#]: Invalid status, received (0x0FFFF), expected (0x1FFFF)!
Also, I should mention that I have verified that the clocks and the SYSREF are being generated on the FMCADC4 board.
To make things more interesting, the same design is working on the Xilinx KCU105 evaluation board.
What are the possible causes of this problem, and how can I debug it?