I am using the EVAL-AD9656 official evaluation board for the AD9656 converter and am trying to integrate it with modern Xilinx JESD204B IP. The issue that arose here is how to provide a SYSREF input to the Xilinx IP core, which expects it to be generated externally. The eval board, as I understand it, does not produce this signal. However, the ADI documentation such as the JESD Survival Guide, on pg. 21 sketch out a nice diagram of how SYSREF is generated and distributed. How should users of the AD9656 supposed to proceed with this?
Thanks for your help!