I have a question about AD9648. Now I am evaluating AD9648 with its EVB kits. The error of ADC sampled data is about 7mV.So we compared with EVB. The error of ADC sampled data is about 6mV.
However, the FPGA on EVB has an algorithm called "Weighting". By using this "Weighting" algorithm, the error will decrease from 6mV to 1mV.
So we wonder how the algorithm “Weighting” in FPGA realizes.
Could you please help with the issue or give some comments on it?